A trivial riscv cpu with tomasulo algorithm implemented in Verilog HDL. Support out-of-order execution and pipline and can run in FPGA with at 100MHz. Simulation of the Tomasulo algorithm using python ...

This repository contains the final project for the CS2957 Computer Architecture course. It features two RISC-V CPU implementations in Verilog: Naive CPU: A classic five-stage pipelined processor.

Abstract: Machine learning has demonstrated remarkable effectiveness in solving scheduling problems through end-to-end optimization. However, dynamic events introduce uncertainty and pose significant ...