Rapidus' new $1.7B infusion; Intel and UMC leadership moves; faster EUV; $100B GPU deal; Arm-Tensor robocar; smartphone ...

Panelists repeatedly highlighted that AI compute scaling is dramatically outpacing traditional Moore’s Law transistor ...

End-to-End Hardware-Driven Graph Preprocessing for Enhanced GNN Performance” was published by researchers at KAIST, Panmnesia ...

Nvidia’s data center revenues have skyrocketed, and hyperscaler capital expenditures soared past $70B in 2025, about double ...

Kalinagaswamy: Both have their own challenges. Scale-up may have hundreds of GPUs or accelerators, and they have to work in a scale-up network. Scale-out is point-to-point. They cannot make that many ...

The industry’s response is to split compute, memory, and I/O across dies, XPU chiplets are pushing toward the reticle limit, and stitch it all together with high‑bandwidth, energy‑efficient die‑to‑die ...

EDA produces a lot of data, but how useful is that for AI to consume? The industry looks at new ways to help AI do a better job.

Designing and deploying DSPs FPGAs aren’t the only programmable hardware option, or the only option challenged by AI. While AI makes it easier to design DSPs, there are rising complexities due to the ...

Cadence’s Mick Posner introduces the Foundational Chiplet System Architecture, a specification that aims to deliver a vendor ...

A new technical paper, “Extreme optical nonlinearities unveiled by ultrafast laser filamentation in semiconductors,” was ...

As packaging complexity rises, the industry faces gaps in data, inspection, and process integration.

The variety of compositions available gives designers many options to achieve the specific properties they need. Indium tin ...